A 10MS/s 11-b 0.19mm2 Algorithmic ADC with Improved Clocking
نویسندگان
چکیده
A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3V supply.
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